Reconfigurable Parallel Image Processing System Using Three-Dimensional LSI

We have proposed a new reconfigurable parallel image processing system in which three-dimensional (3D) LSI is used. A new dynamical multi-context reconfiguration scheme is employed in this system. This scheme can decrease the number of instructions between a reconfigurable processing element array and control RISC processor, and also enable efficient execution of various image processing functions. The proposed image processing system consists of image sensor, frame memory, the coarse-grain dynamically reconfigurable image processor and RISC processor for control and reconfiguration. The reconfigurable processor is tightly coupled with frame memory which is achieved by using 3D LSI. It gives rise to a fully scalable parallel image processing architecture which can provide a new robot vision system with high speed and high flexibility. To achieve such reconfigurable parallel image processing system, we have developed a new three-dimensional integration technology called a super chip integration.